Power consumption in modern electronic devices is a major technological and environmental concern. This is because although technologists are able to reduce the dimensions of the transistor, they are unable to reduce the voltage required for its operation (called supply voltage).
In order to minimize the supply voltage for a transistor, an abrupt transition between the ON to OFF state (and vice versa) is warranted. Unfortunately, these transitions in the conventional MOSFET are thermionic in nature, which restricts the abruptness to the Boltzmann’s limit. Due to this limit, the supply voltage of the transistor is stuck to 1 V.
Tunnel FETs, which rely on tunnelling of charge carriers are the most promising candidates to break the Boltzmann’s limit. However, the same tunnelling mechanism also results in degraded ON state currents.
Researchers at the Centre for Nano Science and Engineering have experimentally demonstrated a novel nano-transistor which combines the operations of both the Tunnel FET and the conventional MOSFET in the same device. This new transistor replaces traditional semiconductors like Silicon with a new class of ‘two-dimensional’ semiconductor (Molybdenum di-Sulphide). Furthermore, innovative CMOS compatible device architecture and materials processing enables the uncovering of new device physics. This invention presents a new paradigm in high performance low power computing for transistors operating in the sub-0.5 V regime.
The work was published in the journal Applied Physics Letters in October 2017 and selected as ‘Editor’s Pick Article.
S Bhattacharjee, KL Ganapathi, S Mohan, Navakanta Bhat, “A sub-thermionic MoS2 FET with tunable transport” Applied Physics Letters 111 (16), 163501, 2017, (Editor’s Pick)
Group Web page: http://nnfc.cense.iisc.ac.in/nano/